1. Field of the Invention
The present invention relates to silicon-on-insulator devices and more particularly, to lateral bipolar transistors formed on silicon-on-insulator structures.
2. Description of the Prior Art
There is renewed interest in fabricating MOSFETs and bipolar transistors on thin silicon films on insulator structures. All such structures have inherent problems that are associated with parasitic circuit elements arising from junction capacitance. These effects become a more severe problem as devices are made smaller. A way to circumvent the problem is to fabricate devices in small islands of silicon on an insulating substrate. In such devices, junction capacitances are minimized, as devices can be placed closer to each other, because isolation is eliminated. In addition, such devices are more resistant to soft errors. Furthermore, silicon-on-insulator devices are potentially faster and more reliable. It is furthermore possible to obtain high performance complementary bipolar devices on such films. The processes for fabrication of bipolar and MOS transistors on silicon-on-insulator (SOI) structures are highly compatible.
The initial approach to fabricating such structures is to grow silicon epitaxially on a substrate of sapphire. An example of such a device can be found in U.S. Pat. No. 4,050,965, which describes the process for the simultaneous fabrication of a CMOS transistor and a bipolar device formed laterally in the epitaxial layer. Another example of a bipolar device formed in a silicon-on-insulator structure can be found in U.S. Pat. No. 4,792,837 which discloses an orthogonal bipolar device in which the base and collector are formed in a first layer of silicon and the emitter is formed in a second layer of silicon deposited directly on the base region. Another lateral bipolar transistor is described by Dennard et al. in IBM Technical Disclosure Bulletin, Vol. 32, No. 6B, November 1989, which discloses an elevated base contact of heavily doped polysilicon formed on the active silicon layer.
An example of the device proposed by Dennard et al. is shown in FIG. 1 herein. FIG. 1 depicts device 10 having a substrate 12 on which is formed an oxide layer 14. A layer of silicon 16 is formed on oxide layer 14 and is lightly doped. The elevated extrinsic base-contact 18 is formed by a deposition of a heavily doped p-type polysilicon film and patterning by lithographic techniques. Patterned photoresist masking techniques are used to introduce p-type doping into layer 16 to form intrinsic base 20, and to introduce n-type doping to form collector 22 and emitter 24. Insulating side wall spacers 26 and 28 are formed on the edges of the extrinsic base contact by well-known insulator deposition and reactive-ion-etching methods.
While the Dennard et al. device has lower base and emitter resistances than conventional structures and most junction capacitances are reduced, thereby improving the device speed, the structure suffers from several drawbacks. The base polysilicon has to be as heavily doped as possible to achieve low base resistance. Furthermore, this doping has to be done before emitter drive-in and the intrinsic base doping. During these steps, there is a potential for the base dopant to diffuse into the lightly doped collector region. In the fabrication of an NPN transistor, it is very difficult to control the p.sup.+ diffusion depth from the polysilicon into the underlying silicon. In a thin SOI film, this problem is aggrevated. A second problem is due to lack of an etch stop for the polysilicon etching step. When the base is patterned, there is no etch stop between the polysilicon and single crystalline silicon, thus there is a possibility of etching into the single crystal silicon film. This is a major problem when thin epitaxial films are used. In addition, the structure has a very large base-collector capacitance, caused by overlap between the heavily doped base and the lightly doped collector.